The present invention relates to ferroelectric memories, and, more particularly, to self-referencing schemes for a 1T/1C ferroelectric memory in which the memory cell itself serves as a reference for determining the stored memory state.
Nonvolatile ferroelectric random access memories (FRAM(copyright)xe2x80x94 trademark of Ramtron International Corporation of Colorado Springs, Colo.) realize the memory function by the use of two different polarization states (generally referred to as xe2x80x9cupxe2x80x9d and xe2x80x9cdownxe2x80x9d polarizations) in the ferroelectric cell capacitors, which are used to distinguish between a logic zero and a logic one data state. It has long been a key issue to build reliable memory references that can be used to distinguish between the two polarization states in a 1T/1C cell structure.
There are two existing types of xe2x80x9cstand-alonexe2x80x9d memory references: voltage references and capacitance references. Both of these types of references are susceptible to the variations in the quality, the dimensions, and the remanent polarizations of the ferroelectric films used in the memory cells. Even for an initially uniform memory array, non-uniform operations on the memory cells introduce substantial fluctuations in the ferroelectric properties of the ferroelectric films in the memory cells, due to uncontrollable effects such as polarization imprint and fatigue in the ferroelectric films. In addition, if the reference cells are built with the same ferroelectric materials, the reference cells will suffer much more imprint and fatigue than memory cells since the reference cells experience many more accesses. This therefore limits the reliability and endurance of the FRAM memory.
In a 1T/1C ferroelectric memory with stand-alone reference cells, one reference is shared by memory cells in a segment or a section. The reference level must be always between the minimum of the bit line voltages corresponding to the logic one data state and the maximum of the bit line voltages corresponding to the logic zero data state among these memory cells. However, both the minimum and the maximum changes with processing variations, temperature, and time. Even for an originally uniform array, the array will lose its uniformity during real operations since cells usually experience different access frequencies. Furthermore, the reference level also shifts with time and temperature. Because of these uncontrollable and unpredictable variations, it is extremely difficult to build a reference that works reliably for all the specified time and temperature ranges.
What is desired, therefore, is a robust self-referencing circuit and method for a 1T/1C ferroelectric memory array that overcomes the inherent performance limitations of the existing stand-alone voltage and capacitive references.
According to the present invention, a circuit and method is disclosed for reading data from a 1T/1C nonvolatile ferroelectric random access memory without using any stand-alone reference circuits. The polarization state in a given 1T/1C memory cell in an array is determined by applying two consecutive plate pulses on the ferroelectric capacitor in the memory cell, preamplifying the bit line voltages corresponding to these two plate pulses, and comparing the preamplified voltages. The two consecutive plate pulses have the same polarity.
The storage information in a ferroelectric memory cell is read out by comparing the responses of the same cell to two consecutive plate line pulses. The self-reference scheme of-the present invention substantially reduces the requirement on the uniformity of the ferroelectric films in the memory cells. All the reliability issues related to stand-alone reference cells are eliminated because no stand-alone reference is used. Thus, the reliability of the memory is substantially enhanced.
In addition, the worst case condition in a 1T/1 C FRAM memory with stand-alone reference cells is when an opposite xe2x80x9cPxe2x80x9d term and an opposite xe2x80x9cUxe2x80x9d term exist in an array because the margin between xe2x80x9cPxe2x80x9d and xe2x80x9cUxe2x80x9d terms becomes minimal in this case. This situation will not be an issue in the self-referencing scheme of the present invention because these two terms are not compared when the ferroelectric capacitor in a memory cell is driven by two plate pulses in the same direction.
Although the self-referencing scheme eliminates the problems mentioned above, the signal margin on the bit lines are as small as those in 1T/1C FRAM memories using stand-alone reference cells. The signal margin on the bit lines decreases as the bit-line-to-cell ratio increases. This puts a limitation on the density of the FRAM memories. However, the present invention provides a way to greatly increase the signal margin by combining the self-referencing scheme with preamplifiers.
There is only one signal path per bit line with the self-referencing scheme of the present invention while there are two signal paths per bit line in a 1T/1C FRAM memory using stand-alone reference cells (one from the bit line and the other from the reference). Thus, a preamplifier can be safely used only with the self-referencing scheme. Using preamplifiers to increase the signal margin is an advantage that uniquely belongs to the self-referencing scheme.
The area efficiency of the memory layout is increased by using the self-referencing scheme and preamplifiers. Firstly, the bit line can be built much longer because of the increased signal margin. Secondly, there are no reference cells with associated control circuits, which add substantial area in a 1T/1C FRAM memory layout.
Operating speed is not reduced when compared to that of an equivalent 1T/1C FRAM memory using stand-alone reference cells. In the self-referencing scheme of the present invention, two plate line pulses are applied to the ferroelectric cell capacitors during a reading operation. In a 1T/1C FRAM memory using stand-alone reference cells, one plate line pulse is applied. However, the time required to pre-charge the reference cells and the reference bit lines plus the time taken by the control circuits for the reference cells may even take longer time than an extra plate pulse.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention, which proceeds with reference to the accompanying drawings.